Flash memory is a commonly used type of non-volatile memory in widespread use as storage for consumer electronics and mass storage applications. Flash memory is pervasive in popular consumer products such as digital audio/video players, cell phones and digital cameras, for storing application data and/or media data. Flash memory can further be used as a dedicated storage device, such as a portable flash drive pluggable into a universal serial port (USB) of a personal computer, and a magnetic hard disk drive (HDD) replacement for example. It is well known that flash memory is non-volatile, meaning that it retains stored data in the absence of power, which provides a power savings advantage for the above mentioned consumer products. Flash memory is suited for such applications due to its relatively high density for a given area of its memory array.
FIG. 1A is a general block diagram of typical flash memory device. Flash memory 2 includes well known input and output buffer circuits, such as input/output (I/O) buffer block 3a and control buffer block 3b for receiving external control and data input signals and providing data output signals. The control buffer block 3b receiving the control signals, such as CE# and WE#, may include other basic logic circuits, for implementing rudimentary functions that may be related to control of the data input and buffers for example. Flash memory 2 includes control circuit 3c, for controlling various high level functions of the flash circuits such as read, program and erase operations for example, an address register 4 for storing address information, a data register 5 for storing program data information, a command register 6 for storing command data information, high voltage circuits for generating the required program and erase voltages, and core memory circuits for accessing the memory array 7. Memory array 7 includes flash memory cells, arranged as NAND cell strings for example. The NAND cell strings of a column are coupled to a bitline, which is connected to a page buffer/sense amplifier circuit 8. Sense amplifier circuit 8 senses read data from a selected page of memory cells and provides program data to a selected page of memory cells. One page of memory cells refers to all the memory cells connected to the same wordline. Driving the wordlines is row drivers/decoders, shown as a row address decoder 9a and row address buffer 9b. There can be one or more stages of decoding, and row address buffer 9b can include block decoding logic.
The control circuit 3c includes a command decoder and logic for executing internal flash operations, such as read, program and erase functions. Those skilled in the art will understand that these operations are executed in response to the command data stored in the command register 6, sometimes in combination with the address data and program data stored in the respective address register 4 and data register 5, depending on the operation to be executed. The command data, address data and program data are issued by a memory controller and latched into the corresponding registers by flash memory 2. The functions of the shown circuit blocks of flash memory 2 are well known in the art. Persons skilled in the art will understand that flash memory 2 shown in FIG. 1A represents one possible flash memory configuration amongst many possible configurations. In FIG. 1A, memory array 7, sense amplifier circuit 8, data register 5, row address decoder 9a and row address buffer 9b are part of one memory bank.
FIG. 1B is a floor plan layout a prior art flash memory device to show the area occupied by various circuit blocks. Typically, all the circuit blocks shown in FIG. 1A are formed in the floor plan layout of FIG. 1B. In FIG. 1B, flash memory chip 10 is a semiconductor material rectangular in shape, upon which are formed transistor circuits and structures. Occupying a large proportion of the area are two memory arrays or memory tiles, 12 and 14, which generally correspond to memory array 7 of FIG. 1A. While the present example flash memory 10 includes two memory arrays, alternative designs can include a single memory array or more than two memory arrays. Located between memory arrays 12 and 14 are row decoders 16 that drive wordlines to the required voltage level for read, program and erase operations. Row decoders 16 generally correspond to row address decoder 9a and row address buffer 9b of FIG. 1A. In the example of FIG. 1B, wordlines (not shown) extend in a horizontal direction. Located below each of memory arrays 12 and 14 are page buffers 18 and 20, each being electrically connected to bitlines (not shown) for providing program data and for sensing read data. Page buffers 18 and 20 generally correspond to data register 5 and sense amplifier 8 of FIG. 1A. The combination of memory array 12, row decoders 16 and page buffer 18 is referred to as a memory bank or plane. Similarly, the combination of memory array 14, row decoders 16 and pager buffer 20 is referred to as another memory bank or plane. The page buffers 18 and 20 receive and provide data via data lines (not shown), which are coupled to the input and output (I/O) circuits in logic block 22. Logic block 22 further includes other circuits such as a command decoder and registers. Another large area is dedicated for a charge pump 24, which is responsible for generating high voltages required for programming and erasing data stored in the flash memory cells of the first memory array 12 and the second memory array 14. Charge pump 24 generally corresponds to the high voltage generator of FIG. 1A. The elements of flash memory chip 10 have been generically described, but persons skilled in the art will understand that each of the outlined blocks of FIG. 1B will include all the circuits necessary to achieve proper operation of flash memory chip 10.
In the presently shown example of FIG. 1B, the flash memory chip 10 is designed to have NAND flash memory cells arranged in NAND cell strings within memory arrays 12 and 14. The NAND cell strings are organized into memory blocks, such as Block[1] to Block[n], where n can be any non-zero integer value. The selection of the number of blocks in each array is a design parameter of flash memory chip 10.
FIG. 2 depicts an example memory array of flash memory chip 10 of FIG. 1B. The example illustrated in FIG. 2 has two memory blocks in one memory array. In FIG. 2, one NAND cell string is outlined with a dashed box 30, which includes a string select device 32, flash memory cells 34, and a sourceline select device 36 connected in series between bitline BL1 and common source line CSL. There can be “i” flash memory cells 34 per NAND cell string, where i is a non-zero integer value. Accordingly, wordlines WL1 to WLi are electrically coupled to corresponding gates of the flash memory cells 34. A string select line (SSL) and a source select line (GSL) are electrically coupled to select devices 32 and 36 respectively. In the present example, all the transistors of the NAND cell string 30 are n-channel devices.
A memory block 38, being the same as memory Block[1] of FIG. 1B for example, will include all the NAND cell strings having select devices and flash memory cells connected to the same wordlines, string select line and source select line. The width of memory block 38 is set by the number of bitlines, which in the case of FIG. 2 is “j” bitlines where j is a non-zero integer value. Memory block 40 includes further NAND cell strings connected to bitlines BL1 to BLj. A bitline and the NAND cell strings electrically connected to it is referred to as a column.
All the circuits of flash memory chip 10 of FIG. 1B, including the NAND cell strings shown in FIG. 2 are formed by using well-known semiconductor manufacturing processes. In such processes, transistors of the same type are grouped together and formed in their own well. For example, n-type transistors are formed in a p-type well and p-type transistors are formed in an n-type well. In some cases, only a single well is used, where its type depends on the type of the substrate. In most NAND flash memory devices, all the NAND cell strings in a memory array are formed in one well, which results in disadvantages that are described later on.
FIG. 3 is a cross-sectional diagram of memory array 14 taken along line A-A′ of FIG. 1B, and angled to show specific features on its surface. The cross-sectional structure of the semiconductor substrate where page buffer 20 and logic block 22 are formed is not shown. In FIG. 3, the substrate 50 is a p-type substrate having an n-well 52 and a p-well 54. P-well 54 is formed within n-well 52 such that p-well 54 is spaced from substrate 50. All the NAND cell strings 30 of FIG. 2, and more specifically the transistor devices of NAND cell strings 30, are formed within p-well 54. The well structure shown in FIG. 3 is commonly known as a triple-well structure, or a triple pocket structure. On the surface of p-well 54 are the NAND cell strings 30, simply represented as trapezoid boxes, where each NAND cell string of a column is connected in parallel to a bitline, such as bitline BLk where “k” is a variable representing a logical bitline position less than BLj. With reference to FIG. 2, the bitline is connected to the string select device 32 of each NAND cell string 30. Accordingly, the NAND cell strings that share common select lines and wordlines are part of one memory block. FIG. 3 illustrates four memory blocks 56, 58, 60 and 62 to simply the drawing, however those skilled in the art will understand that there can be any number of memory blocks in memory arrays 12 and 14. Both the n-well 52 and the p-well 54 receives an erase voltage Verase during erase operations, and are both biased to 0V or VSS during all other operations such as program and read for example. Verase can be coupled to n-well 52 and p-well 54 at multiple different locations.
FIG. 4 is a cross section diagram of a NAND cell string 30 of FIG. 3, having the equivalent circuit diagram shown in FIG. 2. Each flash memory cell includes a polysilicon wordline 70 and a polysilicon floating gate 72, where the floating gate 72 is formed over a thin gate oxide 74. On either side of thin gate oxide 74 and formed within p-type well 54 are n-type diffusion regions 76. The sourceline select device 36 includes a polysilicon gate 78 formed over a thick gate oxide 80, and an n-type diffusion region 82 acting as the common source line CSL. Diffusion region 82 is shared with all the NAND cell strings in the memory block, as illustrated in FIG. 2. The string select device 32 includes a polysilicon gate 84 formed over a thick gate oxide 86, and an n-type diffusion region 88 that is electrically connected to a bitline 90.
As is well known in the art, NAND flash memory devices are block erasable, meaning that individual memory blocks can be selectively erased through Fowler-Nordheim (F-N) tunneling, based on a block address or other selection signal. In order to erase a memory block such as memory block 38 of FIG. 2, the wordlines of the selected memory block are biased to 0V, SSL and GSL are floated, and both the n-well 52 and the p-well 54 are biased to Verase. Verase is a high voltage generated by the charge pump 24 of FIG. 1B, and in example flash memory devices is about 20V. Because SSL and GSL are floated during the erase operation, both SSL and GSL are self-boosted when Verase is applied to n-well 52 and p-well 54 due to the capacitive coupling between the wells and SSL and GSL. Depending on the capacitive coupling ratio, GSL and SSL can be boosted to approximately 80% to 90% of Verase. CSL and all bitlines are floated during the erase operation, and eventually self-boost to about Verase-0.6V. Those skilled in the art will understand that the forward bias p-n junction voltage drop across p-well 54 to the n-type diffusion regions 82 and 88. Under these erase bias conditions, trapped electrons (charge) in the floating gate of the flash memory cells are emitted uniformly to the substrate. The threshold voltage (Vth) of the erased flash memory cell becomes negative, meaning that the erased cell will turn on with a gate bias of 0V.
Since the unselected memory blocks reside in the same p-well 54 as the selected memory block, these unselected memory blocks must be inhibited from being erased. A self-boosting erase inhibit scheme described in U.S. Pat. No. 5,473,563 is widely used in NAND flash memory devices to prevent erasure of unselected memory blocks. To prevent erasure of flash memory cells in unselected memory blocks using the self-boosting erase inhibit scheme, all wordlines in unselected memory blocks are floated. Therefore floated wordlines in the unselected memory blocks are boosted to about 90% of Verase when the p-well 54 rises to Verase, by capacitive coupling between the p-well 54 and the wordlines. It should be understood that the final boosted voltage level on the floating wordlines is determined by the coupling ratio between the substrate and wordlines. The boosted voltage of the wordlines in the unselected memory blocks is effective for reducing the electric field between the p-well 54 and the wordlines, thereby minimizing unintended erasure of data stored therein.
Once the erase operation ends, Verase is set to VSS for a block erase verify operation for determining if all the flash memory cells of the selected memory block have been successfully erased. If not, then a subsequent erase operation is executed upon the selected memory block. Verase is also set to VSS during read and program operations, or alternately, a different circuit couples VSS to n-well 52 and p-well 54. For example, n-channel transistor devices can be used to couple n-well 52 and p-well 54 in response to a control signal that is activated during read or program operations. Logic for executing such an operation would be well known to those skilled in the art. A problem with the prior art NAND flash memory is the amount of time required to drive n-well 52 and p-well 54 from VSS to Verase, which directly affects the total erase time. It is apparent from FIG. 1B that the area of one memory bank is large relative to the total area of flash memory chip 10, and thus the capacitance can be in the range of several nF for example. As a result, the rise time of Verase can be between 200 μs to 300 μs, for example.
FIG. 5 is a graph plotting the relationship between the substrate voltage Vsub and time. If an erase operation begins at time=0 and Verase is at VSS, then there is a delay of t_delay before the substrate voltage reaches Verase. As previously mentioned, this delay can range between 200 μs to 300 μs for some example flash memory devices. A solution to improve erase performance is to increase the size of the charge pump circuit that generates Verase. This typically involves a combination of adding capacitor elements or increasing the size of capacitor elements of the charge pump to increase the rate at which the substrate reaches Verase. A larger charge pump would thus reduce t_delay and improve erase performance. Persons skilled in the art understand that capacitor elements used in such charge pumps occupy significant semiconductor area. FIG. 1B clearly shows that charge pump 24 occupies a significant area of flash memory chip 10, especially in comparison with the logic block 22. An example charge pump circuit is shown in U.S. Pat. No. 5,642,309. In view of the tightly packed layout of the example flash memory chip 10 of FIG. 1B, there is insufficient area for increasing the size of charge pump 24. Accordingly, improved erase performance in flash memory chip 10 may not be attained. In some flash memory chip designs, the primary constraint may be to minimize chip size, which directly impacts the cost of the chip. While a minimally sized charge pump will reduce chip area consumption, the drawback is degraded erase performance. Hence there is a trade-off between erase performance and chip area in prior art flash memory chips.
Another problem with the prior art NAND flash memory is the power consumption due to the charging and discharging of the n-well 52 and p-well 54. As previously mentioned, because each of the memory array wells occupy a large proportion of the area of flash memory chip 10 of FIG. 1B, their capacitance can be in the range of several nF for example. This is problematic because after each erase cycle, an erase verify operation is executed to check that the erased memory cells have the erased threshold voltage. An erase verify operation is similar to a normal NAND flash read operation, and therefore the n-well 52 and p-well 54 are biased to VSS. If the verify operation fails, then the erase cycle is repeated and the wells are charged back to Verase. This process may repeat several times, thus consuming power.
A further problem with the prior art NAND flash memory is the exposure of unselected memory blocks to the Verase well voltage when a selected memory block is to be erased. Although the previously described self-boosting erase inhibit scheme can be used to minimize erase disturbance in the cells of the unselected memory blocks, there is still a voltage difference between Verase of the well and the wordlines that are at about 80% to 90% of Verase in the unselected blocks. While the resulting erase disturb may be small for one erase cycle, the cumulative effect will be significant. For example, if it is assumed that the memory array has 2048 memory blocks and the erase time for one memory block is about 2 ms, then erasing all the memory blocks just once will expose each memory block to 2047×2 ms of erase stress. The cumulative erase disturb stress is more significant in multi-level NAND flash cells.